1. Technical Field
The present invention relates to a data equalizing circuit and a data equalizing method, and more particularly, to a data equalizing circuit of a data receiver circuit and a data equalizing method in a data receiver circuit.
2. Related Art
A data receiver circuit for receiving and outputting data has a data equalizing circuit to correct data transformations occurring in the course of transmitting data.
FIG. 1 is a circuit diagram of a conventional data equalizing circuit.
The conventional data equalizing circuit includes an equalizer 1 and a detection unit 2.
The equalizer 1 corrects data DATA according to a value of a control code EQ_CODE. The detection unit 2 detects a degree of transformation of the data DATA while changing the value of the control code EQ_CODE, and the detection unit 2 outputs a value of the control code EQ_CODE capable of optimally securing a data eye, as a final value. The detection unit 2 detects a degree of transformation of the data DATA according to a scheme of detecting transition positions of the data DATA.
FIG. 2 is a waveform diagram showing a scheme of detecting transition positions of the data DATA in the detection unit 2.
The detection unit 2 divides 1 UI (unit interval) of the data DATA corrected according to the value of the control code EQ_CODE into N periods (ten periods in this case), and counts data transition positions in synchronization with sampling clocks CLK(1) to CLK(10). The sampling clocks CLK(1) to CLK(10) possess the same frequency as the data DATA, and have a phase difference acquired by dividing 1 UI by N. Then, dispersions of counting values are calculated. This is process is performed for all respective values of the control code EQ_CODE while changing the value of the control code EQ_CODE. Finally, the detection unit 2 outputs the value of the control code EQ_CODE which has a largest dispersion value.
In order to more precisely determine a data transition distribution, an increased number of sampling clocks, which have a uniform phase difference, are needed in 1 UI. In this regard, if a number of sampling clocks with a high frequency are generated, a processing burden is imposed on the hardware, and power consumption increases.